Computing devices typically comprise a processor, memory, and a memory controller to provide the processor, as well as other components of the computing device, with access to the memory. The performance of such computing devices is influenced, at least in part, by the memory access latency of the memory subsystem. In general, memory access latency is associated with the time it takes for data to be read from, or written to, memory. In the case of dynamic random access memory (DRAM) for example, the memory access latency can include the time it takes for a memory controller to access a row of DRAM in a bank of memory, which can be highly dependent on the recent accesses to that same memory bank.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation on invention scope is thereby intended.